View W83195BR-341_444243.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W83195BR-341 Data Sheet WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET
-1-
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ..........................................................................................................1 FEATURES ..................................................................................................................................1 PIN CONFIGURATION ................................................................................................................2 BLOCK DIAGRAM .......................................................................................................................3 PIN DESCRIPTION......................................................................................................................3 5.1 Crystal I/O ........................................................................................................................................ 4 5.2 CPU, AGP, PCI Clock Outputs ....................................................................................................... 4 5.3 Fixed Frequency Outputs................................................................................................................ 5 5.4 DRAM Buffer.................................................................................................................................... 5 5.5 I2C Control Interface ....................................................................................................................... 5 5.6 Output Control Pins ......................................................................................................................... 6 5.7 Power an GND Pins ........................................................................................................................ 6 6. 7. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................7 I2C CONTROL AND STATUS REGISTERS ................................................................................8 7.1 Register 0: Frequency Select (Default = 08h) ................................................................................ 8 7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h).......................................... 8 7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) .................................................... 9 7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)......................... 9 7.5 Register 4,5 Reserved..................................................................................................................... 9 7.6 Register 6: M/N Program (Default: 8Bh).........................................................................................9 7.7 Register 7: M/N Program (Default: 2Fh).......................................................................................10 7.8 Register 8: Spread Spectrum Program (Default: 1Fh).................................................................10 7.9 Register 9: Divider Ratio (Default: 03h) ........................................................................................10 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 Register 10: Control (Default: 0Ah)........................................................................................11 Register 11: Control (Default: E7h)........................................................................................12 Register 12: Control (Default: 3Ch) .......................................................................................12 Register 13: Control (Default: 24h) ........................................................................................13 Register 14: Control (Default: 56h) ........................................................................................13 Register 15: Slew Rate Control (Default: 55h) ......................................................................13 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh).......................14 Register 17: Slew Rate Control (Default: CFh) .....................................................................14 Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................14 Register 19: Reserved ...........................................................................................................15 Register 20: Winbond Chip ID - (Ready Only) (Default: 61h)..............................................15 - II -
W83195BR-341
7.21 8. Register 21: Winbond Chip ID - (Ready Only) (Default: 50h)..............................................15
ACCESS INTERFACE ...............................................................................................................16 8.1 Block Write Protocol ......................................................................................................................16 8.2 Block Read Protocol......................................................................................................................16 8.3 Byte Write Protocol........................................................................................................................16 8.4 Byte Read Protocol........................................................................................................................16
9.
SPECIFICATIONS .....................................................................................................................17 9.1 Absolute Maximum Ratings ..........................................................................................................17 9.2 General Operating Characteristics ...............................................................................................17 9.3 Skew Group Timing Clock ............................................................................................................17 9.4 CPU 0.7V Electrical Characteristics .............................................................................................18 9.5 CPU 1.0V Electrical Characteristics .............................................................................................18 9.6 AGP Electrical Characteristics ......................................................................................................18 9.7 PCI Electrical Characteristics........................................................................................................19 9.8 24M, 48M Electrical Characteristics .............................................................................................19 9.9 REF Electrical Characteristics.......................................................................................................19
10. 11. 12. 13.
ORDERING INFORMATION......................................................................................................20 HOW TO READ THE TOP MARKING.......................................................................................20 PACKAGE DRAWING AND DIMENSIONS...............................................................................21 REVISION HISTORY .................................................................................................................22
- III -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
1. GENERAL DESCRIPTION
The W83195BR-341 is a Clock Synthesizer for Intel P4 Springdale/Prescott series chipset and support AMD Athlon processors. W83195BR-341 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, AGP, and PCI clocks setting. All clocks are externally selectable with smooth transitions. The W83195BR-341 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides +/-0.25%, +/-0.5% center type and -0.5%, -1.0% down type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83195BR-341 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. FEATURES
* * * * * * * * * * * * * * * * * 1 pairs differential clock for CPU (P4 or Athlon) 1 pairs differential clock for Chipset 3 AGP clock outputs Support two DDR DIMMS or three SDRAM DIMMS 7 PCI synchronous clocks, 1 free running 1 48 MHz clock outputs for USB 1 24_48 MHz for I/O chip, default 24 MHz 2 REF 14.318MHz clock outputs AGP leads PCICLK from 1.5 nS to 3.5 nS I2C 2-Wire serial interface supports block and byte mode read/write Step-less frequency programming Smooth frequency switch with selections from 66 to 200 MHz Programmable clock outputs Slew rate control and Skew control +/- 0.25% center type spread spectrum in table mode Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Packaged in 56-pin SSOP
-1-
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
3. PIN CONFIGURATION
F S 0 * /R E F 0 GND X IN XOUT VDDAGP AGP0 S E L P 4 _ K 7 * /A G P 1 AGP2 GND & /P C I_ F FS1 & /P C I1 SELSD _D D M U L T S E L * /P C I2 GND P C I3 P C I4 VDDPCI P C I5 P C I6 GND F S 3 & /4 8 M h z F S 2 & /2 4 _ 4 8 M H z V DD48 VDD GND IR E F P D # * /R E S E T # SCLK* SD ATA*
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
V T T _ P W R G D # /R E F 1 VDDR GND C P U T /C P U O D _ T C P U C /C P U O D _ C VDDC VDDI CPUCS_C CPUCS_T GND FBOUT B U F _ IN D D R T 0 /S D R A M 0 D D R C 0 /S D R A M 1 D D R T 1 /S D R A M 2 D D R C 1 /S D R A M 3 VDDD GND D D R T 2 /S D R A M 4 D D R C 2 /S D R A M 5 D D R T 3 /S D R A M 6 D D R C 3 /S D R A M 7 VDDD GND D D R T 4 /S D R A M 8 D D R C 4 /S D R A M 9 D D R T 5 /S D R A M 1 0 D D R C 5 /S D R A M 1 1
#: Active low *: Internal pull up resistor 120K to VDD
&
: Internal Pull-down resistor 120K to GND
-2-
W83195BR-341
4. BLOCK DIAGRAM
FBOUT D D R T (0 :5 )/ S D R A M ( 0 ,2 ,4 ,6 ,8 ,1 0 ) D D R C ( 0 :5 )/ 6 S D R A M (1 ,3 ,5 ,7 ,9 ,1 1 )
6
B U F _ IN
PLL2 D iv id e r X IN XOUT XTAL OSC
2
48M H z 24_48M H z R E F 0 :1
PLL1 S p re a d S p e c tru m
VCOCLK
C P U T /C P U O D _ T C P U C /C P U O D _ C CPU CS_T C PU C S_C
3
M /N /R a tio ROM VTT_PW RGD # F S (0 :3 ) SELP4_K7* SELSD _D D & M U LTSEL* PD #* P C I_ S T O P # * CLK_STO P#*
A G P ( 0 :2 ) D iv id e r P C I_ F
L a tc h & POR
6
P C I 1 :6
C o n tr o l L o g ic & C o n fig R e g is te r
RESET# R re f
IREF
SDATA* SCLK*
I2 C In te rfa c e
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL FUNCTION DESCRIPTION
IN INtd120k INtp120k OUT OD I/O I/OD # *
&
Input Latch input pin and internal 120K pull down Latch input pin and internal 120K pull up Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain Active Low Internal 120k pull-up Internal 120k pull-down
-3-
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
5.1 Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
3 4
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318 MHz nominally with internal loading capacitors (18pF).
5.2 CPU, AGP, PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
53, 52
CPUT/CPUOD_T CPUC/CPUOD_C CPUCS_C, CPUCS_T AGP1
OUT
Current Mode differential clock outputs for P4 CPU or Open Drain Mode differential clock outputs for K7 CPU, selected by hardware trapping power on 7 pin SELP4_K7* selecting. SELP4_K7 = 1 Current Mode, SELP4_K7 = 0 Open Drain Mode.
49, 48
OUT OUT INtp120k OUT OUT INtp120k OUT INtd120k OUT
2.5V differential clock outputs for Chipset. 3.3V 66MHz clock output Power up Latched input to selecting pin 53,52 and 56 output type, SELP4_K7 = 1 the 53,52 is P4 Mode and pin 56 is VTT_PWRGD#, SELP4_K7 = 0 the 53,52 is K7 Mode and pin 56 is REF1.This is internal 120K pull up. 3.3V 66MHz clock output. 3.3V 66MHz clock output. PCI clock stop control pin, This pin is low active. Internal 120k pull up, Selected by Register 1 bit 6 = 0 and Register 9 bit 6 = 1, see Page 10 Table 2. 3.3V 33 MHz free running clock output. Latched input for FS1 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. 3.3V 33 MHz clock output.
7
SELP4_K7* AGP_0 AGP2
6 8
PCI_STOP#* PCI_F
10
FS1& PCI1
11
SELSD_DD& PCI2
Latched input at initial power up for DRAM buffer output type INtd120k selecting, SELSD_DD = 0 DDR Mode SELSD_DD = 1 SDR Mode, This is internal 120K pull down. OUT INtp120k 3.3V 33MHz clock output. Power on trapping for different current reference. The reference current is referred for Pin 25 (IREF), see page 5 Table 1. This pin is latched during VTT_PWRGD#. This pin is internal pull up 120K. 3.3V 33 MHz clock outputs.
12
MULTSEL*
14, 15, 17, 18
PCI [3:6]
OUT
-4-
W83195BR-341
5.3 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
REF0 1 FS0* REF1 56 VTT_PWRGD# 48 MHz FS3& 21 24_48 MHz FS2&
OUT INtp120k OUT IN OUT INtd120k OUT INtd120k
14.318 MHz output. Latched input for FS0 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull up. If SELP4_K7 = 0 this pin is 14.318 MHz output. If SELP4_K7 = 1 this pin is Power good input signal comes from ACPI with low active. This 3.3V input is level sensitive strobe used to determine FS [3:0] and MULTSEL input are valid and is ready to sample. This pin is low active. 48 MHz clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. 24(default) or 48 MHz clock output, select by register 4 bit 7 SEL24 Latched input for FS2 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down.
20
5.4 DRAM Buffer
PIN PIN NAME TYPE DESCRIPTION
45 46
BUF_IN FBOUT
IN OUT
Reference input from chipset. 2.5V input for DDR only mode. 3.3V for standard SDRAM mode. Feedback clock for chipset. Output voltage depends on VDDD Clock outputs. SELSD_DD = 1, these pins are copies of BUF_IN. SELSD_DD = 0, these pins are copies of BUF_IN. Voltage depends on the VDDD. Clock outputs. SELSD_DD = 1, these pins are complementary copies of BUF_IN. SELSD_DD = 0, these pins are copies of BUF_IN. Voltage depends on the VDDD.
44, 42, DDRT[0:5] 38, 36, SDRAM [0, 2, 4, 32, 30 6, 8, 10]
OUT
43, 41, DDRC[0:5] 37, 35, SDRAM [1, 3, 5, 31, 29 7, 9, 11]
OUT
5.5 I2C Control Interface
PIN 28 27
PIN NAME
TYPE I/OD IN
DESCRIPTION Serial data of I2C 2-wire control interface with internal pull-up resistor 120K. Serial clock of I2C 2-wire control interface with internal pull-up resistor 120K.
SDATA* SCLK*
-5-
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
5.6 Output Control Pins
PIN PIN NAME TYPE DESCRIPTION
Deciding the reference current for the CPUT/C pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. The table is show as follows. TABLE 1 25 IREF OUT
MULTSEL Board Target Reference R, Iref (PIN 11) Trace/ Term Z = VDD/(3*Rr) 1 0 50 Ohms 50 Ohms R = 475 1% Iref = 2.32mA R = 221 1% Iref = 5mA Output Current Ioh = 6*Iref Ioh = 4*Iref Ioh @ Z 0.7V @ 50 1.0V @ 50
RESET# 26 PD#*
OD IN
Select by register 1 bit 6 L_MODE if L_MODE = 1 this pin is System reset signal when the watchdog is time out. This pin will generate 250 mS when the watchdog timer is timeout Select by register 1 bit 6 L_MODE if L_MODE = 0 this pin is Power Down Function. This is internal 120K pull up.
5.7 Power an GND Pins
PIN PIN NAME TYPE DESCRIPTION
5 16 22 23 34,40 50 51 55 2, 9, 13, 19, 24, 33, 39, 47, 54
VDDAGP VDDPCI VDD48 VDD VDDD VDDI VDDC VDDR GND
PWR PWR PWR PWR PWR PWR PWR PWR PWR
3.3V power supply for AGP. 3.3V power supply for PCI. 3.3V power supply for 48MHz. 3.3V power supply analog core. 3.3V or 2.5V power for DRAM buffer part. 2.5V power supply for CPUCS_T/C. 3.3V power supply for CPUT/C. 3.3V power supply for REF Ground pin for 3.3 V
-6-
W83195BR-341
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3).
FS4
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU (MHZ) 66.8 99.9 120.2 133.2 72.0 105.1 160.1 140.1 77.0 110.0 180.3 166.6 90.1 99.9 199.8 133.2 160.1 164.0 166.6 169.9 175.1 180.3 184.8 190.0 66.8 100.9 133.6 200.5 66.6 99.9 199.8 133.2
AGP (MHZ) 66.8 66.6 60.1 66.6 72.0 70.1 64.0 70.1 77.0 73.3 60.1 66.6 60.1 66.6 66.6 66.6 80.1 82.0 66.6 67.9 70.0 72.1 73.9 76.0 66.8 67.3 66.8 66.8 66.6 66.6 66.6 66.6
PCI (MHz)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
33.4 33.3 30.0 33.3 36.0 35.0 32.0 35.0 38.5 36.7 30.0 33.3 30.0 33.3 33.3 33.3 40.0 41.0 33.3 34.0 35.0 36.1 37.0 38.0 33.4 33.6 33.4 33.4 33.3 33.3 33.3 33.3
-7-
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
7. I2C CONTROL AND STATUS REGISTERS
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1 Register 0: Frequency Select (Default = 08h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2
SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL
0 0 0 0 1 Enable software table selection FS [4:0]. 0 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output. Software frequency table selection through I2C
1 0
SPSPEN Reserved
0 0
0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable Reserved
7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h)
BIT NAME PWD FUNCTION DESCRIPTION
7
CPUCS_T CPUCS_C L_MODE
1
Pin 48,49 CPUCS_T/C output control Selection for Pin 26. Power Down Input / System Reset Control Output 1: System Reset feature 0: Power Down feature (Default) Pin 53,52 CPUT/C output control Mapping software table. Power on latched value of FS3 (20) pin. Default 0 (Read only) Power on latched value of FS2 (21) pin. Default 0 (Read only) Power on latched value of FS1 (10) pin. Default 0 (Read only) Power on latched value of FS (1) pin. Default 1 (Read only)
6
0
5 4 3 2 1 0
CPUT/C FS4 FS3 FS2 FS1 FS0
1 0 X X X X
-8-
W83195BR-341
7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
PCI_F PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 INV_CPUCS
1 1 1 1 1 1 1 0
Pin 10 PCI_F output control Pin 18 PCI6 output control Pin 17 PCI5 output control Pin 15 PCI4 output control Pin 14 PCI3 output control Pin 12 PCI2 output control Pin 11 PCI1 output control Invert the CPUCS phase, 0: Default, 1: Inverse
7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
PREF1 PREF0 PUSB24 PUSB48 INV_USB48 AGP2 AGP1 AGP0
1 1 1 1 0 1 1 1
Pin 56 REF1 output control Pin 1 REF0 output control Pin 21 24_48 MHz output control Pin 20 48 MHz output control Invert the 48 MHz phase, 0: In phase with 24_48 MHz, 1: 180 degrees out of phase Pin 8 AGP2 output control Pin 7 AGP1 output control Pin 6 AGP0 output control
7.5 Register 4,5 Reserved 7.6 Register 6: M/N Program (Default: 8Bh)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [8] M_DIV [6] M_DIV [5] M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 0 0 0 1 0 1 1
Programmable N divisor value. Bit 7 ~0 are defined in the Register 7.
Programmable M divisor value.
-9-
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
7.7 Register 7: M/N Program (Default: 2Fh)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
0 0 1 0 1 1 1 1 Programmable N divisor value bit 7~0. The bit 8 is defined in Register 6, Bit 7. The bit 9 is defined in Register 9, Bit 7.
7.8 Register 8: Spread Spectrum Program (Default: 1Fh)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 0 1 1 1 1 1 Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0.
7.9 Register 9: Divider Ratio (Default: 03h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
N<9> SEL_CLKSTOP Reserved Reserved Reserved DS2 DS1 DS0
0 0 0 0 0 0 1 1
Programmable N divisor value bit 9 Refer to Table-2 Reserved Reserved Reserved Define the CPU/AGP/PCI divider ratio Refer to Table-3
- 10 -
W83195BR-341
Table-2 Register 1 /bit 6 L_MODE 0 0 1 1 Register 9/bit6 SEL_CLKSTOP 0(default) 1 0 1 PIN 26 PD# PD# RESET# RESET# PIN8 AGP2 PCI_STOP# AGP2 AGP2 PIN18 PCI6 CLK_STOP# PCI6 PCI6
Table-3 CPU, AGP, PCI divider ratio selection Table DS2~DS0 000 001 010 011 100 101 110 111 CPU 2 2 3 4 6 3 4 4 AGP 5 6 6 6 6 7 8 10 PCI 10 12 12 12 12 14 16 20
7.10 Register 10: Control (Default: 0Ah)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
EN_MN_PROG N<10> Reserve Reserve IVAL<3> IVAL<2> IVAL<1> IVAL<0>
0 0 0 0 1 0 1 0
0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Programmable N divisor value bit 10 Reserved
Charge pump current selection
- 11 -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
7.11 Register 11: Control (Default: E7h)
BIT NAME PWD FUNCTION DESCRIPTION
7
CPUT_DRI
1
CPUT output state in during POWER DOWN or Stop mode assertion. 0: Driven (2*Iref), 1: Tristate (Floating) CPUC always tri-state (floating) in power down Assertion. On P4 mode CPU clock output level selection Refer to Page 5 Table-1 Default value follow hardware trapping data on pin12 MULTSEL/PCI2 (Default 1)
6
MULTSEL
X
5 4 3 2 1 0
SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0]
1 0 0 1 1 1 Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8 S
7.12 Register 12: Control (Default: 3Ch)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4
INV_CPU TRI_EN SPSP_TYPE SPSP1
0 0 1 1
Invert the CPU phase 0: Default, 1: Inverse Tri-state all output if set 1 Spread spectrum implementation method 1: Pendulum type 0: Original Spread Spectrum type select. 00: Down 1% 01: Down 0.5% 10: Center 0.5% 11: Center 0.25% CPU to AGP skew control, Skew resolution is 340pS Expand the skew direction is same as CPU_AGP_SKEW [2:0] setting
3
SPSP0
1
2 1 0
ASKEW [2] ASKEW [1] ASKEW [0]
1 0 0
- 12 -
W83195BR-341
7.13 Register 13: Control (Default: 24h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
INV_AGP INV_PCI CSKEW [2] CSKEW [1] CSKEW [0] PSKEW [2] PSKEW [1] PSKEW [0]
0 0 1 0 0 1 0 0
Invert the AGP phase 0: Default, 1: Inverse Invert the PCI phase 0: Default, 1: Inverse CPU to CPUCS skew control, Skew resolution is 340 pS Expand the skew direction is same as CPU_CPUCS_SKEW [2:0] setting CPU to PCI skew control, Skew resolution is 340 pS Expand the skew direction is same as CPU_PCI_SKEW [2:0] setting
7.14 Register 14: Control (Default: 56h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1
CPUCS_S2 CPUCS_S1 USB48_S2 USB48_S1 AGP_S2 AGP_S1 SELP4_K7
0 1 0 1 0 1 X
CPUCS_T/C slew rate control 11: Strong, 00: Weak, 10/01: Normal USB48/DOT48/USB24_48 slew rate control 11: Strong, 00: Weak, 10/01: Normal AGP2, 1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal Device active mode selection 1: P4 mode; 0: K7 mode Default value follow hardware trapping data on pin7 SELP4_K7/AGP1 (Default 1) DRAM module selection 1: SDRAM mode; 0: DDR mode Default value follow hardware trapping data on pin11 SELSD_DD/PCI1 (Default 0)
0
SELSD_DD
X
7.15 Register 15: Slew Rate Control (Default: 55h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
PCI_F_S2 PCI_F_S1 PCI_64_S2 PCI_64_S1 PCI_31_S2 PCI_31_S1 REF_S2 REF_S1
0 1 0 1 0 1 0 1
PCI_F slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI6, 5,4 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI3, 2, 1 slew rate control 11: Strong, 00: Weak, 10/01: Normal REF0, REF1 slew rate control 11: Strong, 00: Weak, 10/01: Norma
- 13 -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
7.16 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
Reserve FBOUT_EN DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
0 1 1 1 1 1 1 1
Reserve FBOUT output control DDRT5, DDRC5 / SDRAM10, 11 output control DDRT4, DDRC4 / SDRAM8, 9 output control DDRT3, DDRC3 / SDRAM6, 7 output control DDRT2, DDRC2 / SDRAM4, 5 output control DDRT1, DDRC1 / SDRAM2, 3 output control DDRT0, DDRC0 / SDRAM0, 1 output control
7.17 Register 17: Slew Rate Control (Default: CFh)
Bit Name
PWD Function Description 1 1 0 0 1 1 1 1 FBOUT slew rate control 11: Strong, 00: Weak, 10/01: Normal CPUODT/C slew rate control 11: Strong, 00: Weak, 10/01: Normal DDR3, 4, 5/SDRAM6, 7, 8, 9, 10, 11 slew rate control 11: Strong, 00: Weak, 10/01: Normal DDR0, 1, 2/SDRAM 0, 1, 2, 3, 4, 5 slew rate control 11: Strong, 00: Weak, 10/01: Normal
7 6 5 4 3 2 1 0
FBOUT_S2 FBOUT_S1 CPUOD_S2 CPUOD_S1 DDR3_S2 DDR3_S1 DDR0_S2 DDR0_S1
7.18 Register 18: M/N Time & Type Control (Default: 5Bh)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
N_Time<2> N_Time<1> N_Time<0> M_Time<2> M_Time<1> M_Time<0> N_TYPE M_TYPE
0 1 0 1 1 0 1 1 Reserved for Winbond internal use, don't modify it Reserved for Winbond internal use, don't modify it M/N mode M value change time control M/N mode N value change time control
Note: This Byte only for Winbond internal and BOIS program use, the release version please reserved this byte.
- 14 -
W83195BR-341
M_Time<2:0> or N_Time<2:0> 000 001 010 011 100 101 110 111 M_Divider or N_Divider timing counter 6.152 S 12.304 S 24.608 S 49.216 S 98.432 S 196.864 S 393.728 S 787.456 S
7.19 Register 19: Reserved 7.20 Register 20: Winbond Chip ID - (Ready Only) (Default: 61h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0 1 1 0 0 0 0 1
Winbond Chip ID. W83195BR-341 (SA5861). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
7.21 Register 21: Winbond Chip ID - (Ready Only) (Default: 50h)
BIT NAME PWD FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
MAS_ID [1] MAS_ID [0] SUB_ID [1] SUB_ID [0] MAS_VER_ID [1] MAS_VER_ID [0] SUB_VER_ID [1] SUB_VER_ID [0]
0 1 0 1 0 0 0 0
MASK definition for master body *A****: 01, *B****: 10, *C****: 11, *D****:00 MASK definition for code body *A****001: 01, *A****002: 10, *A****003: 11, *A****004:00 MASK version definition for master body *A****001AA: 00, *A****001AB: 01, *A****001AC: 10, *A****001AD: 11. MASK version definition for code body *A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D: 11
- 15 -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
8. ACCESS INTERFACE
The W83195BR-341 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR-341 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2.
Block Read and Block Write Protocol
8.1 Block Write Protocol
8.2 Block Read Protocol
## In block mode, the command code must filled 00H
8.3 Byte Write Protocol
8.4 Byte Read Protocol
- 16 -
W83195BR-341
9. SPECIFICATIONS 9.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection (Human body model)
-0.5V to +4.6V -0.5 V to +4.6 V 3.135V to 3.465V 3.135V to 3.465V -65C to +150C -55C to +125C 0C to +70C 2000V
9.2 General Operating Characteristics
VDD = VDDAGP = VDDC = VDDR = VDDPCI = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10 pF
PARAMETER
SYM.
MIN.
MAX.
UNITS
TEST CONDITIONS
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance
VIL VIH VOL VOH Idd Cin Cout Lin
0.8 2.0 0.4 2.4 350 5 6 7
Vdc Vdc Vdc Vdc mA pF pF nH
All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 MHz with load
9.3 Skew Group Timing Clock
VDD = VDDAGP = VDDC = VDDR = VDDPCI = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10 pF
PARAMETER
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
AGP to PCI Skew CPU to CPU Skew AGP to AGP Skew PCI to PCI Skew 48MHz to 48MHz Skew REF to REF Skew
1.5
2.6
3.5 200 250 500 1000 500
nS pS pS pS pS pS
Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V
- 17 -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
9.4 CPU 0.7V Electrical Characteristics
VDDCPU = 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vr = 475, IREF = 2.32 mA, Ioh = 6*IREF
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute Crossing Point Voltages Cycle to Cycle jitter Duty Cycle
175 175 250
700 700 550 150
pS pS mV pS %
100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz
45
55
9.5 CPU 1.0V Electrical Characteristics
VDDCPU = 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vr = 221, IREF= 5mA, Ioh = 4*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute Crossing Point Voltages Cycle to Cycle Jitter Duty Cycle
175 175 510
700 700 760 150
pS pS mV pS %
100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz
45
55
9.6 AGP Electrical Characteristics
VDDAGP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
- 18 -
W83195BR-341
9.7 PCI Electrical Characteristics
VDDPCI= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10 pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
9.8 24M, 48M Electrical Characteristics
VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10 pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Long Term Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 500 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
9.9 REF Electrical Characteristics
VDDR= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
1000 1000 45 -33
4000 4000 1000 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
- 19 -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83195BR-341
56 PIN SSOP
Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83195BR-341 28051234 342GAASA
1st line: Winbond logo and the type number: W83195BR-341 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 342 G A A SA 8051234: wafer production series lot number 3rd line: Tracking code 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: mask version All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 20 -
W83195BR-341
12. PACKAGE DRAWING AND DIMENSIONS
.035 .045
.045 .055 0.40/0.50 DIA
SYMBOL
DIMENSION IN MM
DIMENSION IN INCH
E
END VIEW
HE
A A1 A2 b c D HE E e L L1 Y
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
TOP VIEW
SEE DETAIL "A"
c
D
A2
A
Y SEATING PLANE e b
SIDE VIEW A1 PARTING LINE
0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8
c
0
0
L L1
DETAIL"A"
- 21 -
Publication Release Date: April 13, 2005 Revision 1.1
W83195BR-341
13. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
All of the versions before 0.50 are for internal use. 0.5 0.6 0.7 1.0 1.1 07/07/03 26/8/03 12/18/03 05/04/04 4/13/2005 22 n.a. n.a. 19 First published preliminary version. Some description red text part Correction IC version, Update on web Add disclaimer
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 22 -

▲Up To Search▲

Price & Availability of W83195BR-341

	To Download W83195BR-341 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .